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Verifying super-scalar cores with formal guarantees
Industrial-strength formal verification for production-grade RISC-V SoCs
Tweeted
May 22, 2025
Axiomise
@axiomise Design errors are expensive. Formal verification catches what traditional methods miss, saving you time and money. #Iloveformal #Makingformalnormal
Axiomise
@axiomise Design errors are expensive. Formal verification catches what traditional methods miss, saving you time and money. #Iloveformal #Makingformalnormal
Tweeted
May 20, 2025
Axiomise
@axiomise Just back from an inspiring week at RISC-V Summit Europe 2025 in Paris! We showcased formal verification for RISC-V designs. Thanks to all who visited our booth and @RISC-V International! Let’s make formal together! #RISCv #FormalVerification #Axiomi@RISC-V International! Let’s make formal together! #RISCv #FormalVerification #Axiomiszh
Axiomise
@axiomise Just back from an inspiring week at RISC-V Summit Europe 2025 in Paris! We showcased formal verification for RISC-V designs. Thanks to all who visited our booth and @RISC-V International! Let’s make formal together! #RISCv #FormalVerification #Axiomi@RISC-V International! Let’s make formal together! #RISCv #FormalVerification #Axiomiszh
Tweeted
May 12, 2025
Axiomise
@axiomise Join @AshishDarbari at RISC-V Summit 2025! 🌟 Learn about Making RISC-V Market-Ready. #Iloveformal #R@AshishDarbari at RISC-V Summit 2025! 🌟 Learn about Making RISC-V Market-Ready. #Iloveformal #RISCzFX
Axiomise
@axiomise Join @AshishDarbari at RISC-V Summit 2025! 🌟 Learn about Making RISC-V Market-Ready. #Iloveformal #R@AshishDarbari at RISC-V Summit 2025! 🌟 Learn about Making RISC-V Market-Ready. #Iloveformal #RISCzFX
Tweeted
May 8, 2025
Axiomise
@axiomise Axiomise's footprint® scales beyond 100M gates, finding bugs early! Read our blog:semiengineering.com/how-to-optimiz…JJ
Axiomise
@axiomise Axiomise's footprint® scales beyond 100M gates, finding bugs early! Read our blog:semiengineering.com/how-to-optimiz…JJ
Tweeted
Nov 28, 2024
Axiomise
@axiomise Wishing everyone a Happy Thanksgiving. We express our sincere gratitude to our valued customers, partners, and friends. Your trust and support motivate us daily. May your day be filled with warmth, love, and meaningful moments. Thank you for being an integral part of our journey.
Axiomise
@axiomise Wishing everyone a Happy Thanksgiving. We express our sincere gratitude to our valued customers, partners, and friends. Your trust and support motivate us daily. May your day be filled with warmth, love, and meaningful moments. Thank you for being an integral part of our journey.
Tweeted
Nov 18, 2024
Axiomise
@axiomise Our CEO, Ashish Darbari, joined Brian Bailey to discuss RISC-V’s portability challenges. He highlighted how formal verification exposed critical design flaws in an SoC, leading to re-architecture. Essential for reliable systems! Read moresemiengineering.com/risc-vs-hardwa…Pn
Axiomise
@axiomise Our CEO, Ashish Darbari, joined Brian Bailey to discuss RISC-V’s portability challenges. He highlighted how formal verification exposed critical design flaws in an SoC, leading to re-architecture. Essential for reliable systems! Read moresemiengineering.com/risc-vs-hardwa…Pn
Tweeted
Nov 14, 2024
Axiomise
@axiomise We attended the STEM Women event for graduates yesterday. Our CEO delivered a talk to an audience of future STEM innovators. Thank you to STEM Women for the event. #STEMWomen #STEMGraduates #EmpowerWomen #FutureInnovators #DiversityInSTEM
Axiomise
@axiomise We attended the STEM Women event for graduates yesterday. Our CEO delivered a talk to an audience of future STEM innovators. Thank you to STEM Women for the event. #STEMWomen #STEMGraduates #EmpowerWomen #FutureInnovators #DiversityInSTEM
Uploaded
Oct 4, 2024
5: Making debug faster
5: Making debug faster In this episode of the RISC-V series by Axiomise, we discuss how to make debug smarter and faster. ...
Uploaded
Jun 20, 2024
4. Bug Hunting: From cores to subsystems
4. Bug Hunting: From cores to subsystems In this episode of the RISC-V series by Axiomise, we discuss going beyond core v ...
Uploaded
Jun 14, 2024
3. Overconstraints: Check your blind spots
3. Overconstraints: Check your blind spots In this episode of the RISC-V series by Axiomise, we discuss over-constraints ...
Uploaded
Jun 12, 2024
2. Coverage: Six dimensions
2. Coverage: Six dimensions In this episode of the RISC-V series by Axiomise, we discuss coverage for formal verification ...
Uploaded
Jun 8, 2024
1. From simulation to formal
1. From simulation to formal In the first episode of the RISC-V series by Axiomise, we discuss simulation and the need fo ...
Uploaded
May 7, 2024
RISC-V: You Build, We Verify with Formal Verification
RISC-V: You Build, We Verify with Formal Verification RISC-V is an open-source architecture which anyone can use to build ...
Uploaded
Apr 2, 2024
Axiomise Formal Verification: Meet the Team
Axiomise Formal Verification: Meet the Team In this film, the Axiomise team outlines why they work at Axiomise and why Ax ...
Uploaded
Mar 26, 2024
Why does formal verification matter for semiconductors?
Why does formal verification matter for semiconductors? Axiomise formal verification is about making formal verification ...
Uploaded
Feb 13, 2024
NAVIX Sudoku Solver Using Formal Verification
NAVIX Sudoku Solver Using Formal Verification A demo of NAVIX - a 9X9 Sudoku Solver by Axiomise. Sudoku is a very interes ...
Uploaded
Jan 18, 2024
Hunting down corner-case bugs in RISC-V processors using formal verification
Hunting down corner-case bugs in RISC-V processors using formal verification This talk was given by Dr. Ashish Darbari in ...
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Verifying beyond doubt with formal coverage
Enabling automatic & predictable architectural formal verification for RISC-V
Enabling predictable formal verification in the industry through Axiomise training
Verifying RISC-V designs with high assurance
Verifying RISC-V designs with high assurance
